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Reliability Wearout Mechanisms In Advanced Cmos Technologies (Hb 2009)
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Reliability Wearout Mechanisms In Advanced Cmos Technologies (Hb 2009) Hardcover - 2009

by Strong

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  • Title Reliability Wearout Mechanisms In Advanced Cmos Technologies (Hb 2009)
  • Author Strong
  • Binding Hardcover
  • Edition U.S. Edition
  • Condition Used - Very Good
  • Pages 640
  • Volumes 1
  • Language ENG
  • Publisher John Wiley & Sons, Piscataway, NJ
  • Date 2009-09-01
  • Features Bibliography, Index, Table of Contents
  • Bookseller's Inventory # 9780471731726
  • ISBN 9780471731726 / 0471731722
  • Weight 2.16 lbs (0.98 kg)
  • Dimensions 9.3 x 6.4 x 1.3 in (23.62 x 16.26 x 3.30 cm)
  • Themes
    • Aspects (Academic): Science/Technology Aspects
  • Library of Congress subjects Metal oxide semiconductors, Complementary -
  • Library of Congress Catalog Number 2011377262
  • Dewey Decimal Code 621.397

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From the jacket flap

IEEE Press Series on Microelectronic Systems

Stewart K. Tewksbury and Joe E. Brewer, Series Editors

Reliability Wearout Mechanisms in Advanced CMOS Technologies Alvin W. Strong, Ernest Y. Wu, Rolf-Peter Vollertsen, Jordi Su, Giuseppe LaRosa, Timothy D. Sullivan, and Stewart E. Rauch, III

About the author

ALVIN W. STRONG, PhD, is retired from IBM in Essex Junction, Vermont. He holds nineteen patents, has authored or coauthored a number of papers, and is a member of the IEEE and chair of the JEDEC 14.2 standards subcommittee.

ERNEST Y. WU, PhD, is a Senior Technical Staff Member at Semiconductor Research and Development Center (SRDC) in the IBM System and Technology Group. He has authored or coauthored more than 100 technical or conference papers. His research interests include dielectric/device reliability and electronic physics.

ROLF-PETER VOLLERTSEN, PhD, is a Principal for Reliability Methodology at Infineon Technologies AG in Munich, Germany, where he is responsible for methods and test structures for fast Wafer Level Reliability monitoring and the implementation of fast WLR methods.

JORDI SUNE, PhD, is Professor of Electronics Engineering at the Universitat Autnoma de Barcelona, Spain. He is Senior Member of the IEEE and has coauthored over 150 publications on oxide reliability and electron devices. His research interests are in gate oxide physics, reliability statistics, and modeling of nanometer-scale electron devices.

GIUSEPPE LaROSA, PhD, is Project Leader of the FEOL technology reliability qualification activities for the development of advanced SOI Logic and eDRAM technologies at IBM, where he is responsible for the implementation and development of state-of-the-art NBTI stress and test methodologies.

TIMOTHY D. SULLIVAN, PhD, is Team Leader for metallization reliability at IBM's Essex Junction facility. The author of numerous technical papers and tutorials, he holds thirteen patents with several more pending.

STEWART E. RAUCH, III, PhD, is currently a Senior Technical Staff Member at the IBM SRDC in New York, where he specializes in hot carrier and NBTI reliability of state-of-the-art CMOS devices. He is the author of numerous technical papers and tutorials and holds five patents.

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