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Formal Semantics And Proof Techniques For Optimizing Vhdl Models (Hb)

Formal Semantics And Proof Techniques For Optimizing Vhdl Models (Hb)

Formal Semantics And Proof Techniques For Optimizing Vhdl Models (Hb)
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Formal Semantics And Proof Techniques For Optimizing Vhdl Models (Hb) Hardback - 1999

by Umamageswaran K

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Sp Springer, 1999. New.
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Details

  • Title Formal Semantics And Proof Techniques For Optimizing Vhdl Models (Hb)
  • Author Umamageswaran K
  • Binding Hardback
  • Edition U. S. EDITION
  • Condition New
  • Pages 158
  • Volumes 1
  • Language ENG
  • Publisher Sp Springer
  • Publication date 1999
  • Illustrated Yes
  • Features Bibliography, Illustrated, Index
  • Bookseller's Inventory # CBS-9780792383758
  • ISBN 9780792383758 / 0792383753
  • Weight 0.96 lbs (0.44 kg)
  • Dimensions 9.21 x 6.14 x 0.5 in (23.39 x 15.60 x 1.27 cm)
  • Category Computers - Languages / Programming
  • Library of Congress subjects VHDL (Computer hardware description language)
  • Library of Congress Catalogue Number 98045668
  • Dewey Decimal Code 621.392
  • Quantity available 500

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From the publisher

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

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