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Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models
Stock photo: cover may vary

Formal Semantics and Proof Techniques for Optimizing VHDL Models Hardback - 1998

by Umamageswaran, Kothanda

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Description

Springer, 1998. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. No dust jacket. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,550grams, ISBN:9780792383758
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Details

  • Title Formal Semantics and Proof Techniques for Optimizing VHDL Models
  • Author Umamageswaran, Kothanda
  • Binding Hardback
  • Edition U. S. EDITION
  • Pages 158
  • Volumes 1
  • Language ENG
  • Publisher Springer
  • Publication date 1998
  • Illustrated Yes
  • Features Bibliography, Illustrated, Index
  • Bookseller's Inventory # 4137484
  • ISBN 9780792383758 / 0792383753
  • Weight 0.96 lbs (0.44 kg)
  • Dimensions 9.21 x 6.14 x 0.5 in (23.39 x 15.60 x 1.27 cm)
  • Category Computers - Languages / Programming
  • Library of Congress subjects VHDL (Computer hardware description language)
  • Library of Congress Catalogue Number 98045668
  • Dewey Decimal Code 621.392

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From the publisher

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

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