Stock photo: cover may vary
Instruction Level Parallelism Paperback - 2018
by Aiken, Alex
- Used
- Paperback
- first
NZ$160.58
Free Delivery within USA
Standard delivery: 5 to 10 days
More delivery options
Standard delivery: 5 to 10 days
Dropship order
Ships from Ergodebooks (Texas, United States)
Details
- Title Instruction Level Parallelism
- Author Aiken, Alex
- Binding Paperback
- Edition Softcover reprint of the original 1st ed. 2016
- Condition Used: Good
- Pages 255
- Volumes 1
- Language ENG
- Publisher Springer
- Publication date 2018-06-29
- Illustrated Yes
- Features Illustrated
- Bookseller's Inventory # SONG1493979590
- ISBN 9781493979592 / 1493979590
- Weight 0.87 lbs (0.39 kg)
- Dimensions 9.21 x 6.14 x 0.59 in (23.39 x 15.60 x 1.50 cm)
- Size 6.10x0.64x9.25
- Category Computers - General Information
- Dewey Decimal Code 004.1
- Quantity available 1
About Ergodebooks Texas, United States
Biblio member since 2005
Our goal is to provide best customer service and good condition books for the lowest possible price. We are always honest about condition of book. We list book only by ISBN # and hence exact book is guaranteed.
We have 30 day return policy.
Reader reviews for Instruction Level Parallelism
Write a review for this book
Important Terms and Guidelines
- Please focus on the book’s content and context. Also, add any personal comments as to how you enjoyed the book. Substantiate your likes and dislikes. You may make comparisons to other books.
- Reviews must be at least 140 characters in length.
- Please do not reveal critical plot elements.
- This is not a help line. Contact customer support if you need help.
Your review must not include:
- Obscenities, discriminatory language, or other insulting language not suitable for public domain
- Advertisements, “spam” content, or references to other products, offers or websites.
- Email addresses, URLs, phone numbers, physical addresses or other contact information.
- Overly critical comments about other reviews or reviewers
- Time-sensitive material (i.e. promotional tours, seminars, lectures, etc.)
- Availability, price, or alternative ordering/shipping information
From the publisher
From the rear cover
Since its introduction decades ago, Instruction Level Parallelism (ILP) has gradually become ubiquitous and is now featured in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors. Because these architectures could not exist or (in the case of superscalar machines) cannot achieve their full potential without specific sophisticated compilation techniques to exploit ILP, the development of architectures that support ILP has proceeded hand-in-hand with the development of sophisticated compiler technology, such as Trace Scheduling and Software Pipelining. While essential for achieving the full potential of ILP, in both performance as well as power consumption management, these techniques are still not widely known, in part because of their intricacy and in part because the only widely available references for ILP techniques are the primary resources, with the brevity of introduction common to conference proceedings.
This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.
This book precisely formulates, and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performance as well as area and power minimization of computer designs.
