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Built in Test for VLSI: Pseudorandom Techniques
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Built in Test for VLSI: Pseudorandom Techniques Hardback - 1987 - 1st Edition

by Paul H. Bardell; W. H. McAnney; J. Savir

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From the publisher

This handbook provides ready access to all of the major concepts, techniques, problems and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. The main intention of this book is to present the material in a unified manner, making it a useful source for practising professionals and students alike. It opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, reviewing by comparison the principles of design for testability of more advanced digital technology. It then offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing; and various data compression methods, such as polynomial dividers and unique shift-register sequence generators with special applications.

Details

  • Title Built in Test for VLSI: Pseudorandom Techniques
  • Author Paul H. Bardell; W. H. McAnney; J. Savir
  • Binding Hardback
  • Edition number 1st
  • Edition 1
  • Pages 368
  • Volumes 1
  • Language ENG
  • Publisher Wiley-Interscience, Hoboken, New Jersey, U.S.A.
  • Publication date 1987-10-20
  • Features Index
  • ISBN 9780471624639 / 0471624632
  • Weight 1.46 lbs (0.66 kg)
  • Dimensions 9.58 x 6.39 x 0.88 in (24.33 x 16.23 x 2.24 cm)
  • Category Technology & Industrial Arts
  • Library of Congress subjects Integrated circuits - Very large scale
  • Library of Congress Catalogue Number 87023013
  • Dewey Decimal Code 621.381

About the author

Paul H. Bardell and W. H. McAnney are the authors of Built In Test for VLSI: Pseudorandom Techniques, published by Wiley.

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Built In Test for VLSI: Pseudorandom Techniques

Built In Test for VLSI: Pseudorandom Techniques

by Bardell, Paul H.; McAnney, W. H.; Savir, J

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Built In Test for VLSI: Pseudorandom Techniques
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Built In Test for VLSI: Pseudorandom Techniques

by Bardell, Paul H

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Built In Test for VLSI: Pseudorandom Techniques
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Built In Test for VLSI: Pseudorandom Techniques

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by Bardell, Paul H

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Built In Test for VLSI: Pseudorandom Techniques
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Built In Test for VLSI: Pseudorandom Techniques

by Bardell, Paul H.; McAnney, W. H.; Savir, J

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Built In Test for VLSI: Pseudorandom Techniques
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Built In Test for VLSI: Pseudorandom Techniques

by Bardell, Paul H.; McAnney, W. H.; Savir, J

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Built In Test for VLSI: Pseudorandom Techniques

by Bardell, Paul H.; McAnney, W. H.; Savir, J

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Built In Test for VLSI – Pseudorandom Techniques Techn (Prev.Built–in Pseud Test of Digit Cir)
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Built In Test for VLSI – Pseudorandom Techniques Techn (Prev.Built–in Pseud Test of Digit Cir)

by Bardell, Paul H./ McAnney, William H./ Savir, Jacob

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Built In Test for VLSI
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Built In Test for VLSI

by J. Savir W. H. McAnney Paul H. Bardell

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